Examination apparatus for biological sample and chemical sample

ABSTRACT

A wireless sensor chip suitable for the compact, high-sensitive, and low-cost examination apparatus for easily examining a biological material such as gene at low cost is provided. A sensor chip is formed on an SOI substrate, and an n type semiconductor layer on which a pMOS transistor is formed and a p type semiconductor layer on which an nMOS transistor is formed are isolated by a pn junction. Therefore, the p type semiconductor layer at the outermost portion (chip edge portion to be in contact with solution) is set to floating, and the maximum potential and the minimum potential of the chip are supplied to an n type semiconductor layer and a p type semiconductor layer inside the outermost portion, respectively. Also, the chip is covered with an ion impermeable insulating film for reducing the penetration of positive ions through the oxide layer.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese Patent ApplicationJP 2004-012596 filed on Jan. 21, 2004, the content of which is herebyincorporated by reference into this application.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a sensor and a system, in which thesensor is put into or comes into contact with a sample and resultsthereof are transmitted wirelessly to an external device. As theexamples of the system mentioned above, a system for detectingbiological materials such as nucleic acid, protein, antigen, andantibody and a system for measuring physical and chemical quantity suchas temperature, pressure, light, and ion concentration can be shown.

BACKGROUND OF THE INVENTION

Japanese Patent Laid-Open Application No. 2002-14072 discloses anintegrated circuit device called an integrated sensor device, in which asensor portion, a control unit for processing the signals representingthe detection results of the sensor portion, and an antenna forreceiving the energy required for the communication with outside and thecircuit operation from outside are integrated on one chip. It alsodiscloses that an ion sensitive field effect transistor (hereinafter,referred to as ISFET) and an organic film whose characteristics arechanged when it contacts to gas or liquid containing a substance areused as the sensor portion of this integrated sensor device.

An extended gate structure disclosed in J. van der Spiegel, I. Lauks, P.Chan, D. Babic, “The extended gate chemically-sensitive field effectivetransistor as multi species microprobe, Sensors and Actuators” 4 (1983)pp. 291-298, and K. Tsukada, Y. Miyahara, Y. Shibata, H. Miyagi, “Anintegrated micro multi-ion sensor using platinum-gate field effecttransistors”, Proc. Int. Conf. Solid-State Sensors and Actuators(Transducers '91), San Francisco, USA, 1991, pp. 218-221 is known as astructure suitable for the monolithic integration of the ISFET with theintegrated circuit.

Also, the problem that the device characteristics and the electricinsulation between devices are degraded due to the penetration ofpositive ions into the device forming region in a semiconductorintegrated circuit device with the SOI structure is examined in JapanesePatent Laid-Open Application No. 6-177233, Japanese Patent Laid-OpenApplication No. 6-177242.

SUMMARY OF THE INVENTION

Starting with the gene test and the protein test, the system capable ofeasily measuring biological and chemical materials has been demanded invarious fields. In order to meet such demands, the inventors of thepresent invention examine the wireless sensor chip (hereinafter,referred to as sensor chip) in which a sensor for measuring a biologicalmaterial such as DNA, a chemical material, ion, and physical quantityand a mechanism for wirelessly transmitting the sensing data to theoutside of a chip are integrated on a semiconductor chip. JapanesePatent Laid-Open Application No. 2002-14072 does not describe what typeof device the integrated sensor device can be. Especially, it is desiredthat the device can be manufactured simply by the current semiconductormanufacturing process so as to realize the measurement system at lowcost.

Also, it is also necessary that the device can maintain its reliabilityeven when the sensor chip is used in a solution.

The method for solving the above-described problems is shown below.

A sensor chip is formed on an SOI substrate. However, the n typesemiconductor region in which the pMOS transistor is formed and the ptype semiconductor region in which the nMOS transistor is formed areisolated from each other by the pn junction. This can be achieved byapplying the minimum potential of the sensor chip as the substratepotential of the p type semiconductor region and applying the maximumpotential of the sensor chip as the substrate potential of the n typesemiconductor region.

Also, the integrated circuit constituting the sensor chip is surroundedby an n type (p type) semiconductor region (guard ring) which reachesthe buried insulating layer of the SOI substrate, and its outerperiphery is made to be a p type (n type) semiconductor region. Inaddition, the maximum potential (minimum potential) of the sensor chipis applied to the guard ring, and the semiconductor region of its outerperiphery is set to floating.

Furthermore, in order to prevent the penetration of positive ionsthrough the oxide layer, the chip is covered with an ion impermeableinsulating film.

It is possible to provide a sensor chip suitable for the detection of abiological material such as gene and a chemical material and themeasurement of physical-chemical quantity such as temperature, pressure,and pH.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing the structure of the sensorchip according to the present invention;

FIG. 2 is a block diagram showing the configuration of the wirelesssensing system using the sensor chip;

FIG. 3A is a diagram showing an example of the usage of the sensor chip;

FIG. 3B is an enlarged diagram of a reaction vessel of FIG. 3A;

FIG. 4 is a block diagram showing the configuration of the sensorcircuit using the ISFET as the sensor of the sensor chip;

FIG. 5A is a cross-sectional view of the sensor chip in the wafer level;

FIG. 5B is a plan view of the sensor chip in the wafer level;

FIG. 6 is a cross-sectional view showing the structure assumed when thesensor chip is formed by the bulk CMOS process;

FIG. 7 is a cross-sectional view showing another structure of the sensorchip according to the present invention;

FIG. 8 is a cross-sectional view showing another structure of the sensorchip according to the present invention;

FIG. 9 is a cross-sectional view showing another structure of the sensorchip according to the present invention;

FIG. 10 is a block diagram showing another configuration of the sensorcircuit using the ISFET;

FIG. 11 is a block diagram showing another configuration of the sensorcircuit using the ISFET;

FIGS. 12A and 12B are cross-sectional views showing a part of the sensor(ISFET) of the sensor chip functioning as a DNA chip;

FIG. 13A is a cross-sectional view of the sensor chip using a photodiodeas a sensor of the sensor chip;

FIG. 13B is a circuit diagram showing an example of the light sensorcircuit using the photodiode;

FIG. 14 shows chemical equations of the complementary strand extensionof primer; and

FIGS. 15A to 15G are cross-sectional views showing the process flow formanufacturing the sensor chip of FIG. 1.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. Note that componentshaving the same function are denoted by the same reference symbolsthroughout the drawings for describing the embodiments, and therepetitive description thereof will be omitted.

FIG. 2 shows an example of the measurement system using the sensor chip.First, a sensor chip 200 will be described. A sensor block 150 iscomprised of a sensor such as an ISFET, a thermometer, and a photodiode.It is also possible to use a plurality of sensors or several types ofsensors to form the sensor block 150. A sensor analog block 151 includesa signal processing circuit such as an amplifier for amplifying sensingsignals from the sensor block 150 and an A/D converter for convertingamplified sensing signals to digital signals and a sensor controlcircuit for controlling the sensor block 150. A communication controlcircuit block 152 controls the communication between the sensor chip 200and a reader/writer 230. An RF interface block 153 includes a receivercircuit for receiving signals from the reader/writer 230, a transmittercircuit for transmitting sensing data, and a rectifier for generatingpower and clock. The RF interface block 153 is connected to a coil 155and a resonant capacitor 154 performing the data communication and thepower transmission.

After the sensing data is converted to the digital signal in the sensoranalog block 151, it is converted to the radio frequency signal in theRF interface block 153 and is transmitted to the reader/writer 230through an RF carrier wave. Also, the power consumed in the circuitblocks 150 to 153 mounted on the sensor chip is supplied by theinductive coupling of the reader/writer 230 and an antenna 221.

A measurement control device 231 controls the reader/writer 230 andcollects the sensing data by using the sensor chip 200, and also, itprocesses the sensing data.

FIGS. 3A and 3B show an example of the chip usage in the measurementsystem using the sensor chip. FIGS. 3A and 3B show an example of thechip usage for obtaining the sensing data with the sensor chips beingput into a solution. As shown in FIG. 3A, a computer 260 is used as themeasurement control device 231, and the sensing data is collected fromthe sensor chips 200 through the data/writer 230. A plurality ofreaction vessels 241 are provided in a plate 240. FIG. 3B is an enlargeddiagram of the reaction vessel 241. The sensor chips 200 are put intothe reaction vessel 241 filled with sample solution 242, and thereader/writer side coil 251 provided outside the reaction vessel 241supplies power and transmits control signals to the sensor chips 200 andreceives sensing data from the sensor chips 200. Any of theelectromagnetic wave, change in magnetic field, and change in electricfield can be used for the communication between the sensor chip 200 andthe reader/writer 230.

Hereinafter, an example of a sensor chip using an ISFET as a sensor willbe described. FIG. 4 is a diagram showing an example of a circuitconfiguration provided with a sensor SN included in the sensor block150, an amplifier AMP included in the sensor analog block 151, a biascircuit 174, and a constant current source 175. In this measurement, anion sensitive film 170 and a reference electrode 173 provided on thegate of the ISFET 184 are put into contact with the sample solution 242.The description will be made with taking a pH sensor as an example. Forexample, an Si₃N₄ film (silicon nitride film) can be used as the ionsensitive film 170 in order to make the sensor function as the pHsensor. The Si₃N₄ film is bonded with hydrogen ion (H⁺) in the samplesolution. When an amount of hydrogen ions depending on the hydrogen ionconcentration of the sample solution is bonded to the Si₃N₄ film, itreaches the equilibrium. Meanwhile, the potential of the referenceelectrode 173 is applied as the reference potential of the sourcepotential (substrate potential) of the ISFET 184. The ideal referenceelectrode has such characteristics that the potential distribution atthe interface between the electrode and the solution is not variedregardless of kinds and concentration of the solution. When theconcentration of the hydrogen ions is high relative to the stable sourcepotential, the amount of hydrogen ions to be bonded to the Si₃N₄ film isincreased and the channel resistance of the ISFET 184 is reduced. On theother hand, when the concentration of the hydrogen ions is low, theamount of hydrogen ions to be bonded to the Si₃N₄ film is also reducedand the channel resistance of the ISFET 184 is increased. Therefore, thehydrogen ion concentration of the sample solution can be measured bydetecting the change described above.

The constant current source 175 and the amplifier circuit AMP areprovided in order to detect the above-described change. The drainvoltage Vds of the ISFET 184 is controlled so as to be constant voltagegiven by the constant current source 179 and the resistance 181. Also,since a constant current source 175 and the ISFET 184 are connected inseries, the drain current Ids of the ISFET 184 is constant current. Thedifference between the channel resistance depending on the hydrogen ionconcentration and Vds/Ids is detected as the change of the potential ofa node N1. The hydrogen ion concentration of the sample solution ismeasured by reading the potential of the node N1 from an output terminal180 via a voltage follower amplifier 177.

Note that the bias circuit 174 supplies a predetermined bias potentialto the potential of the reference electrode 173 in order to enhance thedetection sensitivity by the ISFET 184. Also, in order to reduce thepower consumption of the sensor chip, the power supply of the constantcurrent source 174 and the bias circuit 174 is stopped by a sensorcontrol circuit (not shown) when the sensor is not operated.

In order to detect the potential of the node N1 by using the circuitshown in FIG. 4, it is necessary that the high impedance exists betweenthe node N1 and the node N2. Meanwhile, in order to form the device atlow cost, the device is preferably composed of bulk CMOS. It is assumedthat the sensor chip is composed of standard bulk CMOS for thecomparison with the sensor chip of this embodiment. FIG. 6 is across-sectional view of the sensor chip composed of bulk CMOS. Thedetailed description thereof will be omitted here. However, since thenode N1 is a well 106 and the high impedance exists between the node N1and the node N2, this well is set to floating. Since the sensor chip isnot resin-sealed, that is, used as a so-called bare chip for the costreduction, an electrode 131 corresponding to the reference electrode 173and a substrate 118 are short-circuited by the sample solution.Therefore, the inventor found out that the sensor chip simply composedof standard bulk CMOS cannot maintain the high impedance between thenode N1 and the node N2. As described above, it is necessary to preventthe short circuit between an electrode and a semiconductor region via asample solution in the case of the sensor chip to be used in the samplesolution.

FIG. 1 shows a sectional structure of the sensor chip of the presentinvention. An ISFET is used as a sensor and the sensor (ISFET) and awireless communication device are formed on the same semiconductorsubstrate as described in FIG. 2. The sensor chip includes two ISFETs,and the first ISFET has an ion selection film 134 for selectively takingthe target ions and the second ISFET has an ion selection film 135 forselectively taking the target ions different from those taken by thefirst ISFET. Due to the difference in ion selectivity, the amount ofions taken from the sample solution into the films differs between thefirst ISFET and the second ISFET, and the potential of the gates inrespective ISFETs differs from each other. By measuring this as thedifference in the channel conductance (resistance) of the ISFETs, theion concentration of the sample solution can be obtained. The advantageof this structure will be described later with reference to FIG. 10.

It is desired that the change for the standard CMOS process is reducedto minimum so as to achieve the cost reduction and the structure withhigh reliability capable of electrically isolating the substrate fromthe sample solution can be obtained. Therefore, an SOI (Silicon onInsulator) substrate is used as the semiconductor substrate to realizethe electric isolation of the chip rear surface. In addition, withrespect to the edge of the chip, a guard ring as an impurity diffusionlayer which reaches the buried insulating layer (buried oxide layer:hereinafter, referred to as BOX layer) of the SOI substrate is formed onthe periphery of the chip, and a p type or n type impurity diffusionlayer is formed inside the guard ring. Also, the impurity diffusionlayer on the outer periphery of the guard ring is set to floatingpotential and the potential of the impurity diffusion layer inside theguard ring is set to the reverse bias potential relative to thepotential of the impurity diffusion layer of different conductivitytype. By doing so, the insulation structure by the pn junction can beobtained.

Also, the reduction of the penetration of positive ions through theexposed portion of the oxide film is also important for the enhancementof the device reliability. When an exposed portion of the oxide film ispresent on the edge of the chip, positive ions such as sodium penetrate.For example, in the structure shown in FIG. 6, the positive ionspenetrate through the interlayer insulating film 120, 122, or 124 madeof silicon oxide (SiO₂) exposed at the edge and cause the degradation ofcharacteristics of the device formed on the semiconductor substrate 118such as the threshold voltage of the MOS transistor and the leakagecharacteristics of the pn junction. Since it is assumed that the sensorchip is used as an unpackaged chip in order to achieve the costreduction, it is necessary to prevent the penetration of positive ionsin the chip level.

As described above, in order to satisfy the requirement to use theunpackaged chip in a solution, the following two conditions areimportant for the enhancement of the reliability of a sensor chip. Thatis, the first is to insulate the rear surface and the edge of the chipfrom the solution, and the second is to prevent the penetration ofpositive ions through the edge of the chip.

As shown in FIG. 1, the sensor and each circuit block are formed on theSOI substrate 100. On the SOI substrate, a single crystal silicon layer(p type, 10 Ωm) with a thickness of 2 μm is formed on the BOX layer. ThenMOS transistor (the term “MOS transistor” is used as a generic term ofan insulating-gate field effect transistor) is formed in the p type well110 and the pMOS transistor is formed in the n type well 107. These MOStransistors are transistors used in the circuit blocks 151 to 153 inFIG. 2. Also, the ISFET constituting the sensor has the same gatestructure as that of the nMOS transistor. The potential of the gate 117of the ISFET is set to floating and is connected to the ion sensitivefilm 134 or the reference ion sensitive film 135 via the wiring layers121, 123, and 130. The structure of the ISFET described above suitablefor the multilayer wiring structure is called an extended gate structure(see, Japanese Patent Laid-Open Application No. 2002-14072 and JapanesePatent Laid-Open Application No. 6-177233), and it has an advantage thestandard process for forming a MOS transistor can be used with almost nochange. Of course, the structure in which the ion sensitive films 134and 135 are arranged directly on the gate 117 can be used as thestructure of the ISFET.

The adjacent nMOS are isolated from each other by a field insulatingfilm 114. In the example shown in FIG. 1, the field insulating film hasa thickness not reaching the BOX layer, for example, 450 nm. Asdescribed above, the MOS transistors of the same conductivity type areisolated by a field insulating film. Furthermore, the MOS transistors ofdifferent conductivity types are isolated by a field insulating film andby setting the potentials of the n well and p well in which each of theMOS transistors is formed so as to reversely bias the pn junction. Atthis time, when it is assumed that the thickness of the field insulatingfilm is 450 nm, the thickness of the field insulating film below themain surface of the silicon substrate is 200 nm and the thickness of thefield insulating film above the main surface of the silicon substrate is250 nm. Since the depth of the well diffusion layer is about 1000 nm,the well diffusion layer is provided below the field insulating film anda plurality of MOS transistors are formed in the same well.

A first wiring layer 121 and a second wiring layer 123 are formed afterforming the MOS transistors. Next, an ion impermeable insulating film125 is deposited on an oxide insulating film 124. At this time, theoxide insulating films 120, 122, and 124 in the chip peripheral portionare removed to expose the silicon layer 109 before depositing the ionimpermeable insulating film 125. Then, by depositing the ion impermeableinsulating film 125, the ion impermeable insulating film 125 and thesilicon layer 109 come into contact with each other at silicon layerexposed portions 127 and 128 in the chip peripheral portion, and thediffusion path of the positive ions of the oxide insulating films 120,122, and 124 is shut.

Phosphosilicate glass (PSG) or silicon nitride (Si₃N₄) can be used asthe ion impermeable insulating film 125. The PSG has a function tocapture the positive ions diffused into the oxide insulating film byusing phosphorus. In the example of FIG. 1, a silicon nitride film witha thickness of 150 nm is used as the material scarcely permeating ions.The silicon nitride has an advantage that it is superior in waterresistance in comparison to PSG.

After forming the ion impermeable insulating film 125, an insulatingfilm 126 is deposited and a metal layer for forming a connection portion130 to the ion sensitive films 134 and 135, a coil 132, and a pseudoreference electrode 131 is formed. Copper of 10 μm is used as the metallayer. The pseudo reference electrode is an electrode for applying areference potential to the gate of the ISFET with reference to thesolution potential when sensor chips are put into the solution(reference electrode 173 in FIG. 4). Although the potential distributionat the interface between an electrode and a solution is not varied dueto the kinds and the concentration of the solution in the case of theideal reference electrode, a normal hydrogen electrode or an Ag—AgClelectrode approximately satisfying the condition is used as theelectrode in practice. However, these electrodes are not suitable fromthe viewpoint of the compatibility with the process of forming thesemiconductor integrated circuit. Therefore, a material at leastchemically stable to the solution is used for the reference electrodethough it does not completely satisfy the condition that the potentialdistribution at the interface between the electrode and the solution isnot varied (for this reason, that is, because it is not an idealreference electrode, the term of “pseudo” reference electrode is used.).

For example, gold with a thickness of 100 nm is formed after forming anadhesive metal layer to copper. Before forming metal layers 130, 131,and 132, the insulating layers 123, 125, and 126 are processed to formthrough holes, and the necessary connection to the integrated circuitportion is made. After forming the metal layers 130, 131, and 132, aninsulating film 133 is deposited and a through hole is formed in a partof the gate connection electrode 130 of the ISFET. Then, the ionsensitive films 134 and 135 connected to the gates of the first ISFETand the second ISFET are formed, respectively. FIGS. 5A and 5B show thestate where the chips shown in FIG. 1 are formed on a wafer (the areaincluding two chips is illustrated). FIG. 5A is a cross-sectional viewand FIG. 5B is a plan view. However, FIG. 5B shows the layout of theseveral layers (semiconductor regions) that cannot see in the completedproduct. A region 105R is the guard ring, a region 109 is a outerperipheral region of the guard ring, and contact regions 127 and 128between the ion impermeable insulating film 125 and the region 109 arepresent on the region 109. After forming the integrated circuit, thesensor, the coil, and the ion sensitive film to complete the wafer, itis diced at the scribe region (separation region) 140 into respectivechips.

The electric isolation of the sensor chip will be described based on thesensor chip shown in FIG. 1 and FIGS. 5A and 5B. The electric isolationon the chip rear surface is achieved by the BOX layer 102. Also, theelectric isolation on the chip side surface can be achieved by thestructure described below. That is, it can be achieved by the structurein which the conductivity type of the silicon layer 103 is made to be ptype, a p type impurity diffusion layer 109 is arranged around the chip,and an n type impurity diffusion layer 105R (guard ring) which reachesthe BOX layer 102 is arranged inside the p type impurity diffusion layer109. The n type impurity layer 105 is formed as a diffusion layer formedunder the ion implantation and diffusion conditions that make itpossible to have the diffusion depth which reaches the BOX layer 102. Asshown in FIG. 5B, the guard ring 105R is arranged along the chipperiphery and is connected to the maximum potential in the chip. The ptype impurity diffusion layer on the outer periphery thereof is set toelectrically floating. The p type substrate 108 inside the guard ring105R and the p type well 110 of the nMOS transistor are set to theground potential of the chip, and the n type well 107 of the pMOStransistor and the deep n type impurity diffusion region 105 are set tothe maximum potential of the chip. The power supply voltage used in theintegrated circuit is used as the maximum potential of the chip, forexample, it is set to 3V.

Therefore, even when the potential of the p type floating layer 109 isincreased by the potential of the sample solution, since the guard ringlayer 105R and the floating layer 109 are reversely biased, theinsulation between the sensor chip and the solution can be maintained asfar as within the power supply voltage. Also, the ground potential ofthe chip differs by only the bias potential 174 on the basis of thepseudo reference electrode 173. When the bias potential generated in theintegrated circuit of the chip is set lower than the power supplypotential, the insulation of the integrated circuit is not lost. Notethat, for setting the floating layer 109 to n type, the guard ring isset to p type and the ground potential of the chip is set thereto.

Also, the polarity of the impurity diffusion layer is not limited to thedescription above. For example, even in the case where the sensor chipis formed on the n type SOI substrate, the same effects can be obtainedby giving the suitable polarity of a diffusion layer and well potential.

Next, the reduction of diffusion of the positive ions from the chip edgewill be described. First, the diffusion path of the positive ions willbe described. In the portion above the main surface of the SOI substrate100, the diffusion path of the positive ions through the oxideinsulating film from the chip edge portion is shut by the ionimpermeable film 127. In addition, the BOX layer 102 can be cited as asilicon oxide film formed below the main surface of the SOI substrate,and the BOX layer 102 can be the diffusion path of the positive ions. Asdescribed in the structure of FIG. 1, since the thickness of the fieldinsulating film 114 which isolates the devices is smaller than that ofthe silicon layer 103, the field insulating film 114 does not reach theBOX layer 102. Therefore, the BOX layer 102 is isolated from the oxidelayer formed above the main surface of the SOI substrate 100, and thus,the positive ions diffused through the BOX layer 102 into the substratedo not reach the devices constituting the integrated circuit formed onthe main surface of the substrate. Also, as the region which may beinfluenced by the positive ions diffused into the BOX layer, there arethe p type well 110 of the nMOS transistor, the n type well 107 in whichthe pMOS transistor is formed, and the deep n type isolation layer 105for isolating the p type well layer. However, in these regions, the ptype well is fixed to the minimum potential, and the n type well and thedeep n type isolation layer are fixed to the maximum potential asdescribed above. Therefore, the influence of the positive ions in theBOX layer does not reach the channel region of the MOS transistor whichoperates the integrated circuit and the region of the n/p type diffusionlayers which constitute the source and drain, and the diffusion layerresistor.

As described above, the structure of the MOS transistor and the ISFETshown in FIGS. 1 and 5 is identical to that not using the SOI substrate,and the structure unique to the SOI substrate is unnecessary. Therefore,it can be manufactured through the usual process for the general-purposesubstrate. In addition, with respect to the layout, it is not necessaryto fix the well potential in each MOS transistor, and similar to thebulk CMOS, it is preferable that the contact portion to the wiring forsetting the potential is provided at any optional parts in the commonwell including a plurality of MOS transistors. Furthermore, with respectto the device isolation and the setting of the well potential, it ispossible to design the integrated circuit based on the layout rulesimilar to that of the normal silicon substrate without the SOIstructure. Consequently, since it is possible to use the process for thegeneral-purpose transistor and the conventional circuit design data, thehighly stable and reliable sensor chip excellent in chip insulationcharacteristics can be provided at low cost and in a short amount oftime.

FIG. 7 is a cross-sectional view showing the first modified example ofthe device structure of the sensor chip. The difference from thestructure in FIG. 1 is that the trench deeper than the BOX layer 102 isformed in the peripheral portion of the chip before the deposition ofthe ion impermeable insulating film 125, and the ion impermeableinsulating film 125 is deposited thereon. By doing so, the ionimpermeable insulating film 125 directly contacts to the SOI supportsubstrate 101. Therefore, the electric isolation of the chip edge can beachieved by the ion impermeable insulating film 125, and also, thediffusion path of the positive ions is shut by the ion impermeableinsulating film 125. The characteristics of this structure is that theBOX layer 102 is also separated from the chip edge. Therefore, it ispossible to reduce the diffusion of positive ions into the chip throughthe chip edge. Hence, when this structure is used, the influence of thepositive ions diffused into the BOX layer 102 can be prevented even inthe structure shown in FIG. 4 in which the potential of the well 190varies.

FIG. 8 is a cross-sectional view showing the second modified example ofthe device structure of the sensor chip. The difference from thestructure in FIG. 1 is that the thickness of the field insulating film119 is made equal to or larger than that of the silicon film on the BOX.By doing so, the MOS transistor is isolated by the insulating film, andhence, it is possible to improve the breakdown voltage of the deviceisolation and the breakdown voltage of the latch-up between MOStransistors. However, if the positive ions are diffused from the BOXlayer 102 in this structure, the device characteristics are adverselyaffected. Therefore, the structure similar to that of FIG. 7 is used asthe structure around the chip. More specifically, since the portionaround the chip is isolated by the ion impermeable insulating film 125,the problem of the diffusion of positive ions does not occur.

In this modified example, the structure in which the field insulatingfilms 118 and 119 reach the BOX layer is used, and such a structure canbe achieved in the following manner. That is, (1) the silicon layer 103on the BOX layer 102 is made thinner. For example, the thickness of thesilicon layer 103 is set to 150 nm and that of the field insulating filmis set to 450 nm (the thickness below the main surface of the SOIsubstrate is set to 200 nm). (2) The thickness of the silicon layer 103is set to 2 μm and a deep trench is formed in the device isolationregion and an insulating film is deposited thereon. (3) The thickness ofthe silicon layer 103 is set to 500 nm and that of the field insulatingfilm is set to 1.5 μm. For example, when the method of (1) is used, thesource and drain regions 111, 112, and 113 of the MOS transistor comeinto contact with the BOX layer 102, Therefore, it becomes possible toreduce the parasitic capacitance between the source and drain regionsand the silicon layer or that between the wiring on the field insulatingfilm and the silicon layer, and thus, the reduction of power consumptionand the increase of the operation speed of the integrated circuit can beachieved.

FIG. 9 is a cross-sectional view showing the third modified example ofthe device structure of the sensor chip. This structure is characterizedin that metal wiring 129 is used to shut the diffusion path of thepositive ions from the chip edge. In the outer region of the region inwhich the integrated circuit and the sensor are arranged, the diffusionpath of positive ions of the interlayer insulating film made of siliconoxide is shut by using the metal wiring and the interlayer through hole.For example, the diffusion path of the positive ions can be shut byproviding the ring-shaped wirings in the outer periphery of the chip andforming the ring-shaped through holes which connects the ring-shapedwirings in the different wiring layers. According to this structure, itis possible to achieve the structure that can shut the diffusion path ofpositive ions without any particular changes for the process of formingthe normal MOS transistor. Note that it is also possible to combine thestructure in which the path of positive ions is shut by the use of metalwiring and the structure in which the path of positive ions is shut bythe use of an ion impermeable insulating film.

Similar to the device of FIG. 1, the electric insulation on the chipedge in the device of FIG. 9 is achieve by the pn junction composed ofthe guard ring 105R formed of an n type impurity layer fixed to themaximum potential and the p type impurity layer 109 with the floatingpotential. Alternatively, it is also possible to achieve the insulationby forming a deep trench structure in the periphery of the chip andusing an ion impermeable insulating film similar to the structures ofFIGS. 7 and 8.

The device structures of FIGS. 1, and 7 to 9 show the examples in whichthe first ISFET and the second ISFET having the ion sensitive films withdifferent ion selectivities are provided. As described above, forexample, in the structure shown in FIG. 1, since the well of the nMOStransistor is fixed to the power supply potential and the well of thepMOS transistor is fixed to the ground potential, it can be said thatthe influence of the positive ions diffused through the BOX layer issmall. However, in the case of the structure of an amplifier for theconstant drain voltage and the constant drain current as shown in FIG.4, the n type well 108 in which the ISFET is formed is connected to theground potential through the high-impedance current source 175 and ischanged to the potential at which the drain current set by the currentsource 175 depending on the potential of the gate 170 of the ISFET canpass. More specifically, since the p well in which the ISFET is formedcannot be fixed to the ground potential, there is the possibility thatit is influenced by the positive ions diffused from the BOX layer.

Therefore, in order to further reduce the influence of the positiveions, the sensor circuit as shown in FIG. 10 is formed by using areference ISFET 185. The sensor circuit in FIG. 10 is provided with afirst sensor circuit SNC1 and a second sensor circuit SNC2, and they areoperated by the common reference electrode 173 and bias voltage 174. Theoperation of the first and second sensor circuits SNC is similar to thatof the sensor circuit in FIG. 4. Here, the ISFET 184 (first ISFET) ofthe first sensor circuit SNC1 is the measurement ISFET having asensitive film which selectively captures the target ions and molecules,and the ISFET 185 (second ISFET) of the second sensor circuit SNC2 isthe reference ISFET having a sensitive film with the selectivity for theions and molecules different from those of the first ISFET 184. It ispossible to cancel the influence of the positive ions by detecting theoutput difference between the first sensor circuit SNC1 and the secondsensor circuit SNC2 by using a comparator 189.

As another circuit configuration, it is possible to use an amplifierwith a differential pair as shown in FIG. 11. In the configuration ofFIG. 4, since the well of the ISFET is set to floating, there is thepossibility that the influence of the positive ions from the BOX layeris caused. Since the p type well potential is fixed to the groundpotential in the configuration shown in FIG. 11, it is possible toeliminate the influence of the positive ions from the BOX layer.

In the foregoing, the pH sensor is taken as an example in thedescription of the sensor chip according to the present invention.However, the sensor chip achieved by the present invention is notlimited to the pH sensor. For example, the DNA sensor is also achievedin the same manner. FIG. 12 shows the partial structure of the ISFET inthe case of the DNA sensor. In the case of the pH sensor, a sensitivefilm with the ion selectivity is deposited on the gate of the ISFET,whereas a metal layer 300 is deposited on the gate of the ISFET and aprobe DNA 301 is attached to the metal layer 300 in the case of the DNAsensor. It is necessary that the metal layer 300 is formed of a materialto which the probe DNA can be easily attached. For example, gold isavailable. A target DNA is bonded specifically to the probe DNA of theDNA chip. Since the DNA has a negative charge, the potential of theISFET is changed when the target DNA and the probe DNA are bondedspecifically. By using this change, the existence of the target DNA inthe sample solution can be detected in the same manner as that of the pHsensor.

When forming the reference ISFET as shown in FIG. 10, two structures areavailable, that is, (1) a probe DNA with the base sequence differentfrom that of the probe DNA of the measurement ISFET is attached onto thegate of the reference ISFET, and (2) the probe DNA is not attached ontothe gate of the reference ISFET. From the viewpoint of the easiness offorming the device, the structure of (2) is more advantageous. In thiscase, the metal to which the probe DNA can be easily attached is used asthe metal layer 300 for the gate of the measurement ISFET, and the metalto which the probe DNA is hardly attached is used for the gate of thereference ISFET.

Furthermore, it is also possible to detect an organic material such asprotein by using the sensor chip according to the present invention.When protein does not have either of positive and negative charges, thepreliminary process in which the protein to be detected is modified bythe charge is performed in advance. By doing so, when the protein isspecifically bonded to the ISFET due to the antigen-antibody reaction,the gate potential of the ISFET is changed. In this manner, it ispossible to detect the organic material in the sample solution.

Further, not only the ISFET but also other sensors such as a temperaturesensor, a photodiode, and a strain sensor are also available. Thestructure of the sensor chip using the photodiode as a sensor is shownin FIG. 13A. The photodiode is formed of a p type layer 141 and an ntype layer 142, and each circuit block described in FIG. 2 is integratedon the sensor chip.

An example of the light sensor circuit using the photodiode is shown inFIG. 13B. First, φres is set in an on state (set to “H”). Thereby, thereset MOS transistor 151 connected to the photodiode 150 is turned on,and the node PD(1) is charged by the reset potential Vpd0. After thecharge, the reset MOS transistor 151 is in an off state and thephotodiode 150 is set to the charge storing mode to start the storage ofthe light signals from the sample. With the passage of time, thepotential of the node PD(1) is gradually reduced from the resetpotential Vpd0 depending on the incoming light amount. When the signalstorage time has passed, the voltage reduction amount of the output nodeVout is read via the source follower MOS transistor 152. In this manner,the light amount can be measured.

The photodiode can be used as the sensor of a measurement usingbioluminescence such as the SNPs (single nucleotide polymorphismsanalysis) of the DNA based on the BAMPER (Bioluminometry) method. In theBAMPER (Bioluminometric Assay with Modified Primer Extension Reactions)method, it is designed that the 3′ end of the primer DNA is located atthe position to detect the displacement and then the complementarystrand synthesis is initiated. The complementary stand extension of theprimer is significantly influenced by whether or not the 3′ end matcheswith the target, and when it matches with the target, the complementarystrand extension occurs. However, when it does not match with thetarget, the complementary strand extension scarcely occurs. Thediscrimination in SNPs is performed by using this. The chemical equationthereof is shown in FIG. 14.

More specifically, PPi (inorganic pyrophosphate) is formed as theby-product of the DNA complementary strand synthesis of the reactionsubstrate dNTP (deoxynucleotide triphosphoate) in the presence of theDNA polymerase. When this is reacted in the presence of APS (adenosine 5phosphosulfate) and ATP sulfurylase, the ATP is produced. Since the ATPemits a light when it is reacted in the presence of luciferin andluciferase, the complementary strand extension is detected by measuringthe light. Since the inorganic pyrophosphate is produced by thelight-emitting reaction, the light emission is continued while consumingthe APS. The light emission resulting from the complementary strandextension is detected by the photodiode.

An example of the process flow for forming the structure of FIG. 1 isshown in FIGS. 15A to 15G. FIGS. 15A to 15G are cross-sectional viewseach showing the step of the manufacturing process.

In the step of FIG. 15A, an SOI substrate for forming the device isformed. Here, the thickness of the BOX layer is 0.5 μm, and theconductivity type of a silicon layer on the BOX layer is p type, thespecific resistance thereof is 10 Ωcm, and the thickness thereof is 1.5μm.

In the step of FIG. 15B, a field insulating film for the deviceisolation is formed A silicon nitride film is patterned so as todetermine the region of the field insulating film. The oxide film isformed by the thermal treatment at 110° C. in the wet oxidizingatmosphere. The oxidation time is controlled so that the oxide film hasthe thickness of 450 nm.

In the step of FIG. 15C, windows of resist are formed in the isolationregion between the wells and the insulation region around the chip.Thereafter, phosphorus ions are implanted for forming a deep n typeimpurity diffusion layer which reaches the BOX layer and the diffusionat 1200° C. for 120 minutes is performed. Subsequently, the resist ispatterned and boron/phosphorus which are the impurities of the p/n typewells are ion-implanted. Thereafter, the thermal diffusion at 1100° C.for 50 minutes is performed.

In the step of FIG. 15D, a MOS transistor is formed. First, BF₂ foradjusting the threshold voltage is ion-implanted. Next, an oxide filmwith a thickness of 25 nm to be the gate insulating film of the highbreakdown voltage MOS transistor is formed by the thermal treatment inthe wet oxidizing atmosphere at 850° C. Subsequently, the high breakdownvoltage gate oxide film located at the position where a normal breakdownvoltage MOS transistor is to be formed is removed and a gate oxide filmwith a thickness of 8 nm is formed by the thermal treatment at 800° C.in the wet oxidizing atmosphere. Then, polysilicon and tungsten silicideto be the gate are deposited and processed into the shape of the gate.Thereafter, as the impurity for relaxing the electric field, phosphorusis ion-implanted into the nMOS region and boron is ion-implanted intothe pMOS region, and then, the thermal treatment at 850° C. for 10minutes is performed. In order to form a high-concentration impuritylayer to be the source and drain, arsenic is ion-implanted into the nMOSregion and BF₂ is ion-implanted into the pMOS region, and then, it isannealed at 850° C for 20 minutes.

In the step of FIG. 15E, a wiring and an interlayer insulating film areformed. First, a first layer wiring is formed and then a silicon nitridelayer and a silicon oxide layer to be the insulating films with the MOStransistor are deposited. Thereafter, the patterning for forming thecontact holes is performed. Subsequently, a barrier layer made oftitanium nitride and tungsten is deposited, and thereafter, aluminum isdeposited and patterned to form the wiring. Next, as an insulating filmwith a second layer wiring, a silicon oxide film is deposited andthrough holes for connecting the wirings are formed, and then, a barrierlayer made of titanium nitride and tungsten is deposited. Thereafter,aluminum is deposited and patterned to form the wiring. Then, a thirdlayer wiring is formed in the same manner.

In the step of FIG. 15F, a silicon nitride film is formed as aprotection film (ion impermeable film), the patterning of the padportion for the coil is performed and then the passivation film on thepad is removed.

In the step of FIG. 15G, copper to be the communication coil is formedby plating. The ion sensitive film is formed in the openings connectedto the gate of the ISFET according to need.

The present invention can be applied to a sensor chip for easilyexamining a biological material such as gene and physical-chemicalquantity and to a measurement system for performing the examination byusing the sensor chip.

1. A semiconductor integrated circuit device formed on an SOI substrate,comprising: a first semiconductor region of second conductivity typewhich is formed on said SOI substrate and in which a plurality of MOStransistors of first conductivity type are formed; a secondsemiconductor region of first conductivity type which is formed on saidSOI substrate and in which a plurality of MOS transistors of secondconductivity type are formed; a plurality of wirings formed on saidfirst and second semiconductor regions; and an oxide layer forelectrically isolating said wirings or said wirings from said SOIsubstrate, wherein sidewalls of said oxide layer are covered with an ionimpermeable insulating film.
 2. The semiconductor integrated circuitdevice according to claim 1, wherein a first potential is supplied tosaid first semiconductor region and a second potential is supplied tosaid second semiconductor region, thereby applying reverse bias to a pnjunction between said first semiconductor region and said secondsemiconductor region, and said first potential is one of maximumpotential and minimum potential of said semiconductor integrated circuitdevice and said second potential is the other of maximum potential andminimum potential of said semiconductor integrated circuit device. 3.The semiconductor integrated circuit device according to claim 2,further comprising: a third semiconductor region of second conductivitytype which is formed so as to reach a buried insulating layer of saidSOI substrate and surround said integrated circuit; and a fourthsemiconductor region of first conductivity type formed on an outerperiphery of said third semiconductor region, wherein said secondpotential is supplied to said third semiconductor region and said fourthsemiconductor region is set to floating.
 4. The semiconductor integratedcircuit device according to claim 1, wherein said plurality of MOStransistors of first conductivity type formed in said firstsemiconductor region are isolated by a plurality of first fieldinsulating films, said plurality of MOS transistors of secondconductivity type formed in said second semiconductor region areisolated by a plurality of second field insulating films, and thicknessof said first and second field insulating films is smaller than thatfrom a main surface of said SOI substrate to a buried insulating layer.5. The semiconductor integrated circuit device according to claim 1,wherein said ion impermeable insulating film covers also an outerperiphery of a buried insulating layer of said SOI substrate.
 6. Thesemiconductor integrated circuit device according to claim 5, whereinsaid plurality of MOS transistors of first conductivity type formed insaid first semiconductor region are isolated by a plurality of firstfield insulating films, said plurality of MOS transistors of secondconductivity type formed in said second semiconductor region areisolated by a plurality of second field insulating films, and said firstfield insulating film and said second field insulating film reach theburied insulating layer of said SOI substrate.
 7. The semiconductorintegrated circuit device according to claim 1, wherein metal wiringsand through hole patterns for preventing penetration and diffusion ofions from outer periphery of said oxide layer are provided.
 8. Thesemiconductor integrated circuit device according to claim 1, wherein anion sensitive field effect transistor is provided.
 9. The semiconductorintegrated circuit device according to claim 1, wherein aphosphosilicate glass layer or a silicon nitride layer is used as saidion impermeable insulating film.
 10. A sensor chip, comprising: a sensorportion; a signal processing circuit for processing sensing signals fromsaid sensor portion; a communication control circuit for controlling acommunication with an external device; an interface circuit forconverting said sensing signals processed in said signal processingcircuit into radio frequency signals; and a coil and a resonantcapacitor for transmitting said radio frequency signals to said externaldevice, wherein said sensor portion, said signal processing circuit,said communication control circuit, said interface circuit, and saidcoil and resonant capacitor are integrated on a chip, said sensor chipis formed on an SOI substrate, a plurality of wirings formed on said SOIsubstrate and an oxide layer for electrically isolating said wirings orsaid wirings from said SOI substrate are formed, and sidewalls of saidoxide layer are covered with an ion impermeable insulating film.
 11. Thesensor chip according to claim 10, further comprising: a firstsemiconductor region of second conductivity type which is formed on saidSOI substrate and in which a plurality of MOS transistors of firstconductivity type are formed; and a second semiconductor region of firstconductivity type which is formed on said SOI substrate and in which aplurality of MOS transistors of second conductivity type are formed,wherein a first potential is supplied to said first semiconductor regionand a second potential is supplied to said second semiconductor region,thereby applying reverse bias to a pn junction between said firstsemiconductor region and said second semiconductor region, and saidfirst potential is one of maximum potential and minimum potential ofsaid sensor chip and said second potential is the other of maximumpotential and minimum potential of said sensor chip.
 12. The sensor chipaccording to claim 11, further comprising: a third semiconductor regionof second conductivity type which is formed so as to reach a buriedinsulating layer of said SOI substrate and surround said integratedcircuit; and a fourth semiconductor region of first conductivity typeformed on an outer periphery of said third semiconductor region, whereinsaid second potential is supplied to said third semiconductor region andsaid fourth semiconductor region is set to floating.
 13. The sensor chipaccording to claim 11, wherein said plurality of MOS transistors offirst conductivity type formed in said first semiconductor region areisolated by a plurality of first field insulating films, said pluralityof MOS transistors of second conductivity type formed in said secondsemiconductor region are isolated by a plurality of second fieldinsulating films, and thickness of said first and second fieldinsulating films is smaller than that from a main surface of said SOIsubstrate to a buried insulating layer.
 14. The sensor chip according toclaim 11, wherein said ion impermeable insulating film covers also anouter periphery of a buried insulating layer of said SOI substrate. 15.The sensor chip according to claim 10, wherein said sensor chip is usedin contact with a sample solution in an unpackaged state,
 16. Ameasurement system, comprising: reaction vessels; a reader/writer; anantenna connected to said reader/writer; and sensor chips put into saidreaction vessels, wherein said sensor chip can receive signals from saidantenna or transmit sensing data to said reader/writer via said antenna,said sensor chip is formed on an SOI substrate, a plurality of wiringsformed on said SOI substrate and an oxide layer for electricallyisolating said wirings are formed, and sidewalls of said oxide layer arecovered with an ion impermeable insulating film.
 17. The measurementsystem according to claim 16, wherein said sensor chip is used incontact with a sample solution in an unpackaged state.
 18. Themeasurement system according to claim 16, wherein said sensor chipincludes: a first semiconductor region of second conductivity type whichis formed on said SOI substrate and in which a plurality of MOStransistors of first conductivity type are formed; and a secondsemiconductor region of first conductivity type which is formed on saidSOI substrate and in which a plurality of MOS transistors of secondconductivity type are formed, a first potential is supplied to saidfirst semiconductor region and a second potential is supplied to saidsecond semiconductor region, thereby applying reverse bias to a pnjunction between said first semiconductor region and said secondsemiconductor region, and said first potential is one of maximumpotential and minimum potential of said sensor chip and said secondpotential is the other of maximum potential and minimum potential ofsaid sensor chip.
 19. The measurement system according to claim 18,wherein power of said sensor chip is supplied by inductive coupling ofsaid antenna and a coil of said sensor chip.
 20. The measurement systemaccording to claim 18, wherein said sensor chip includes: a thirdsemiconductor region of second conductivity type which is formed so asto reach a buried insulating layer of said SOI substrate and surroundsaid integrated circuit; and a fourth semiconductor region of firstconductivity type formed on an outer periphery of said thirdsemiconductor region, and said second potential is supplied to saidthird semiconductor region and said fourth semiconductor region is setto floating.
 21. The measurement system according to claim 18, whereinsaid sensor chip is characterized in that said plurality of MOStransistors of first conductivity type formed in said firstsemiconductor region are isolated by a plurality of first fieldinsulating films, said plurality of MOS transistors of secondconductivity type formed in said second semiconductor region areisolated by a plurality of second field insulating films, and thicknessof said first and second field insulating films is smaller than thatfrom a main surface of said SOI substrate to a buried insulating layer.22. The measurement system according to claim 18, wherein said ionimpermeable insulating film covers also an outer periphery of a buriedinsulating layer of said SOI substrate.